Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
In a computing system, a processing core associated with a virtual memory system outputs a virtual memory address (also referred to herein as virtual address) on a logical memory space when the processing core has to access instruction and/or data. However, the actual instruction and/or data are stored at a physical memory address (also referred to herein as physical address) on a physical space (e.g., on any appropriate storage unit). Therefore, the virtual address has to be translated to the corresponding physical address, before accessing the physical space. In various computer systems, a translation look-aside buffer (TLB), which stores mapping from virtual addresses to physical addresses, is used for the translation.